The MG32F02U128AD support multiple and flexible communicate interface for production application. It
provides alternate function pins those are including of GPIO, I2C, SPI, UART, Timer with IC/PWM, ADC,
Analog Comparator, DAC, EMB, NCO, CCL and SWD(on chip debug). It has maximum 73 GPIO pins and
provides programmable IO type – quasi-bidirectional , push-pull output , open-drain output , input only(Hi-z) with
optional pull-high. In addition, it is built-in internal de-bounce circuit to deglitch noise for worse signals.
- CPU Core
- ARM 32-bit Cortex-M0 CPU
- Operation frequency up to 48MHz
- Built-in one NVIC for 32 external interrupt inputs with 4-level priority
- Built-in one 24-bit system tick timer
- Built-in one single-cycle 32-bit multiplier
- Built-in one SWD serial wire debugger with 2 watch points and 4 breakpoints
- Flash Memory
- Built-in embedded max. 128K bytes flash memory for application code
- Support ICP (In-circuit program) for ISP boot code update through SWD interface
- Support ISP (In-system program) for application code update
- â–¬ Support programmable ISP flash memory size for ISP boot code
- Support IAP (In-application program) for application data update
- â–¬ Support programmable IAP flash memory size
- SRAM Memory
- Built-in embedded max. 16K bytes SRAM
- â–¬ Support private 2K bytes for DMA and 14K bytes for software to improve access performance
- Built-in extra 512 bytes SRAM for USB endpoints’ packet buffer.
- Power
- Built-in two embedded regulators for core logic power and USB analog macro
- Built-in brown-out detectors
- â–¬ BOD0 detect 1.4V
- â–¬ BOD1 detect by selected level 4.2V/3.7V/2.4V/2.0V
- â–¬ BOD2 detect 1.7V
- Built-in a power management controller with power-down and wakeup control
- Support three power operation modes
- â–¬ ON(Normal) mode and SLEEP , STOP power down modes
- Support wake-up from SLEEP/STOP modes via multiple sources
- Reset
- Built-in embedded POR (power-on reset) circuit
- Built-in one reset source controller
- â–¬ Programmable chip cold reset and warm reset for reset source
- â–¬ Independent software reset control for internal modules
- Provide multiple reset source
- â–¬ POR/BOD/External reset pin input/Software force reset
- â–¬ IWDT/WWDT/ADC/Analog Comparator
- â–¬ Illegal address error reset/Flash access protect error reset
- â–¬ Missing clock detect (MCD) reset
- Clock
- Built-in embedded ILRCO (internal low frequency RC oscillator) by 32KHz
- Built-in embedded IHRCO (internal high frequency RC oscillator)
- ▬ Trimmed to 11.059 or 12MHz ±1% at +25℃
- Built-in embedded PLL clock output for system clock
- Built-in embedded XOSC oscillator with MCD for external 32KHz and 4 ~ 25MHz
- Support external clock input up to 36MHz
- Built-in a clock source controller with independent clock enable control for modules
- Support internal XOSC oscillator and internal ILRCO/IHRCO clock output
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