Megawin 8051 MCU MG82F6B001AS8

1-T 80C51 Central Processing Unit

•  Stack Pointer warning indicator

MG82F6B001 with 8K Bytes Flash ROM & 512 Bytes EEPROM

• ISP memory zone could be optioned as 0.5KB/1.0KB~3.5KB
• 512 Bytes EEPROM write/erase cycle: 100,000
• Flexible IAP size by software configured
• Code protection for Flash memory access
• Flash write/erase cycle: 20,000
• Flash data retention: 100 years at 25°C
• Default MG82F6B001 Flash space mapping

• AP Flash default mapping (6.5KB, 0000h~19FFh)

  IAP Flash default mapping (Disabled)

  ISP Flash default mapping (1.5KB, 1A00h~1FFFh), ISP Boot code

  Data RAM: 1K Bytes

• On-chip 256 bytes scratch-pad RAM
• 768 bytes expanded RAM (XRAM)
• Support page select on XRAM access  Dual data pointer

• Interrupt controller

•  12 sources, four-level-priority interrupt capability
• Two external interrupt inputs, nINT0, nINT1 with glitch filter
• All external interrupts support High/Low level or Rising/Falling edge trigger

• Total 7/8 (with split mode) timers in MG82F6B001

•  RTC Timer and WDT Timer
• Timer 0, Timer 1, Timer 2
•  PCA0, Program Counter Array 0
•  S0 BRG
• If Timer 2 in split mode, MG82F6B001 has total 8 timers

• Three 16-bit timer/counters, Timer 0, Timer 1, Timer 2

• Synchronous control of Run-Enable, Stop and Reload on Timer 0~2
• New 6 operating modes in Timer 2 with 8 clock sources and 8 capture sources
• Timer 2 can be split to two 8-bit timers
• Clock Count Output (CCO) on T2CKO
• Timer 0~2 support PWM mode
• Timer 2 support Duty Capture function